Bare Die Improves:
Size & Weight
Designers of space-constrained systems face the challenge of determining how to incorporate expanding functional needs into reduced spaces in a timely and cost-effective manner. For many handheld, portable, and other small form factor products, silicon packaging has become the major size-limiting element of their design layout. The conversion from standard semiconductor packaging to unpackaged die provides the system designer with opportunities for more efficient use of limited space. At the same time, bare die implementation affords improved electrical performance, better signal integrity, and higher levels of integration with reduced weight and height. These benefits allow designers to overcome the challenges of small form factor applications. The implementation in die form of a standard dual PLL can reduce space consumption by greater than 50%. The implementation rate of die products is rapidly increasing as a result of both application form factor needs and system performance improvement requirements. The main customer application drivers in the migration from packaged semiconductor die to wire bond die include:
The lower inductance and capacitance of bare die is important in analog, RF, and power applications. Signal propagation and power/ground distributions are also improved.
Size and Weight
Improvements vary based on the current packaging in use.
The reduced number of interconnects with die use leads to improved reliability. The typical packaged part has three connection points per 1/O. Compare this with only two for wire bonds.
Lower Cost of Ownership
This is most notable in high volume applications where density is required and high yield silicon is implemented. The lower cost of ownership takes into consideration substrate,
assembly, system test, equipment utilization, rework, and increased product value. In addition, the cost of a die product is typically lower than the package equivalent.
These die advantages promote higher levels of integration using existing mature products, lead to increased functionality per square area, and reduce costs. Additionally, performance improvements are achieved with no additional cost penalty. Integrating die for SiP (System-in-Package) solutions provides a benefit over both standard package solutions and SOC (System-on-Chip) solutions. As design cycle time requirements continue to shorten and product time to market becomes increasingly important, die for SiP solutions finds greater utility in meeting the designer’s needs.
Reference: TI / Introduction To Die & Wafer Products